The development of semiconductor switching technology for high power applications in motor drive circuits, appliance controls and lighting ballasts, for example, began with the bipolar junction transistor. As the technology matured, bipolar devices became capable of handling large current densities in the range of 40-50 A/cm.sup.2, with blocking voltages of 600 V. Despite the attractive power ratings achieved by bipolar transistors, there exist several fundamental drawbacks to the suitability of bipolar transistors for all high power applications. First of all, bipolar transistors are current controlled devices and a large control current into the base, typically one fifth to one tenth of the collector current, may be required to maintain the device in an operating mode. Even larger base currents, however, are typically required for high speed forced turn-off. These characteristics make the base drive circuitry complex and expensive. The bipolar transistor may also be vulnerable to breakdown if a high current and high voltage are simultaneously applied to the device, as commonly required in inductive power circuit applications, for example. Furthermore, it may be difficult to parallel connect these devices since current diversion to a single device may occur at high temperatures, making emitter ballasting schemes necessary.
The power MOSFET was developed to address this base drive problem. In a power MOSFET, a gate electrode bias is applied for turn-on on and turn-off control. Turn-on occurs when a conductive inversion-layer channel is formed in series between the MOSFET's source and drain regions under appropriate bias. The gate electrode is separated from the device's active area by an intervening gate insulator, typically silicon dioxide. Because the gate is insulated from the active area, little if any gate current is required in either the on-state or off-state. The gate current is also kept small during switching because the gate forms a capacitor with the device's active area. Thus, only charging and discharging current ("displacement current") is required. The high input impedance of the gate, caused by the presence of the gate insulator, is a primary feature of the power MOSFET. Moreover, because of the minimal current demands on the gate, the gate drive circuitry can be easily implemented on a single chip. As compared to bipolar technology, the simple gate control typically provides for a large reduction in cost and a significant improvement in reliability. These benefits may be offset, to some extent, by the typically high on-state resistance of the MOSFET's active region, which arises from the absence of minority carrier injection. As a result, a power MOSFET's operating forward current density may be limited to relatively low values, typically in the range of 10 A/cm.sup.2, for a 600 V device, as compared to 40-50 A/cm.sup.2 for the bipolar transistor.
Because of these features of bipolar transistors and MOSFETs, hybrid devices which combine bipolar current conduction characteristics with MOS-controller current flow were developed and found to provide significant advantages over single technologies such as bipolar or MOSFET alone. One example of a hybrid device is the insulated-gate bipolar transistor (IGBT). The IGBT combines the high impedance gate of the power MOSFET with the small on-state conduction losses of the power bipolar transistor. An added feature of the IGBT is its ability to block both forward and reverse bias voltages. One embodiment of an IGBT is disclosed in an article by inventor B. J. Baliga and M. S. Adler, R. P. Love, P. V. Gray and N. Zommer, entitled "The Insulated Gate Transistor: A New Three Terminal MOS Controlled Bipolar Power Device," IEEE Trans. Electron Devices, ED-31, pp. 821-828 (1984), the disclosure of which is hereby incorporated herein by reference. Based on experimental results, on-state losses were shown to be greatly reduced when compared to power MOSFETs. This was caused by conductivity modulation within the IGBT's drift region during on-state conduction. Moreover, very high conduction current densities in the range of 200-300 A/cm.sup.2 were also achieved. Accordingly, an IGBT can be expected to have a conduction current density approximately 20 times that of a power MOSFET and five (5) times that of an equivalent bipolar transistor. Typical turn-off times for IGBTs can also be in the range of 10-50 .mu.s. These and other aspects of IGBTs are more fully described in U.S. Pat. No. 5,412,228 to Baliga, entitled "Multifunctional Semiconductor Switching Devices Having Gate-Controlled Regenerative and Non-Regenerative Conduction Modes, and Methods of Operating Same", assigned to the present assignee, the disclosure of which is hereby incorporated herein by reference.
The basic structure of a DMOS-based IGBT is shown in cross-section in FIG. 1A. In the IGBT, forward conduction can occur by positively biasing the collector with respect to the emitter and applying a positive gate bias of sufficient magnitude to invert the surface of the P-base region under the gate. By creating an inversion layer in the P-base region, electrons are allowed to flow from the N+ emitter region into the N-type drift region (shown as N-). In this forward conducting state, the junction J2 is forward biased and the P+ collector region injects holes into the drift region. As the forward bias across the collector/drift region junction is increased, the injected hole concentration increases until it exceeds the background doping level in the drift region. In this regime of operation, the device operates like a forward-biased P-i-N diode with heavy conductivity modulation of the N-type drift region. Accordingly, the IGBT can operate at high current densities even when designed for operation at high blocking voltages. As long as the gate bias is sufficiently large to produce enough inversion layer charge for providing electrons into the drift region, the IGBT forward conduction characteristics will look like those of a P-i-N diode. However, if the inversion layer conductivity is low, a significant voltage drop will begin to appear across this region like that observed in conventional MOSFETs. At this point, the forward current will saturate and the device will operate in its active or current saturation region, as shown in FIG. 1B. Referring now to FIG. 1C, the basic structure of a DMOS-based FET is illustrated. The illustrated DMOS FET is similar to the IGBT of FIG. 1A, however, N-type drain and source regions replace the P-type collector and N-type emitter regions, respectively.
Due to the strong depletion region pinch-off effect (i.e., "JFET effect") between the adjacent P-base regions in the devices of FIGS. 1A and 1C, a selective implant step is typically performed to increase the doping concentration in the upper portion of the drift region commonly referred to as the "neck" region. Thus, after implant, respective "JFET" regions are formed between adjacent P-base regions. In the case of high voltage IGBTs fabricated using very lightly doped drift regions, the JFET effect can lead to an undesirable snap-back in the on-state characteristics unless the JFET implant has sufficient dose. However, too large a JFET implant dose can result in a degradation in the forward blocking voltage characteristics of the device. Accordingly, attempts have been made to form IGBTs and related devices which do not require the formation of JFET regions to prevent parasitic snap-back.
In particular, FIG. 2 illustrates a conventional IGBT structure which has an insulated-gate electrode within in trench. Such devices have been shown to have superior on-state characteristics due to an enhancement in the hole/electron distribution profile in the drift region. The trench-based IGBT of FIG. 2 can be fabricated by using conventional DMOS processing techniques, as illustrated by the process flow diagram of FIG. 3. Preferred techniques to form trench-based power devices are also described in U.S. Pat. Nos. 5,742,076 to Sridevan et al., entitled "Silicon Carbide Switching Devices Having Near Ideal Breakdown Voltage Capability and Ultralow On-State Resistance"; and. U.S. Pat. No. 5,637,898 to Baliga, entitled "Vertical Field Effect Transistors Having Improved Breakdown Voltage Capability and Low On-State Resistance", assigned to the present assignee, the disclosures of which are hereby incorporated herein by reference.
Referring now to FIGS. 2-3, conventional techniques for forming DMOS-based devices having trench gate electrodes, Block 100, typically include the steps of forming a semiconductor substrate containing a relatively lightly doped drift region extending to a surface thereof, Block 102. This substrate may comprise a P-type substrate (shown as P+) and a buffer layer (shown as N+) may be provided between the P-type substrate and the drift region (shown as N-). As will be understood by those skilled in the art, the buffer layer is provided to inhibit reach-through breakdown. Steps are then performed to selectively implant dopants of first and second conductivity type into the drift region and then diffuse the implanted dopants to form an emitter/source region within a base region well (shown as P-base), Block 104. A more highly doped base contact region (not shown) may also be formed in the base region so that majority carriers (e.g., holes) collected by the base region can be provided to an emitter electrode. Next, an photolithographically defined etching can be performed to etch through the emitter/source region and base region to define a trench in the substrate, Block 106. This series of steps is also illustrated by FIGS. 2A-2C of the aforementioned '898 patent. Then, with respect to Block 108, an insulated gate electrode is formed in the trench. This insulated gate electrode may be formed by depositing a gate insulating layer (e.g., SiO.sub.2 layer) on the surface of the substrate and in the trench, and then depositing a blanket layer of polycrystalline silicon ("polysilicon") on the deposited gate insulating layer. As will be understood by those skilled in the art, the channel length of the device is determined by the vertical distance between the diffused emitter/source region and the diffused base region, as measured along a sidewall of the trench. In other words, the channel length equals the distance between the emitter/base region P-N junction and the base region/drift region P-N junction. Next, a planarization step, using such techniques as chemical-mechanical polishing (CMP), is performed to expose the base and emitter/source regions at the surface, Block 110. Contacts are then made to the exposed base and emitter regions, Block 112.
Unfortunately, these steps typically used to fabricate trench-based devices are more complex than those for the conventional planar DMOS process. In addition to the need to form vertically walled trenches having small trench width (for high integration levels), it is essential to fill the trench without voids in the polysilicon and then planarize the polysilicon to expose the base and emitter/source regions. However, the planarization step is typically the yield limiting step because the top surface of the polysilicon must not only lie below the surface of the substrate, but also above the bottom edge of the emitter/source region diffusion at the P-N junction with the base region. Yet, because of the small depth of the emitter/source region (typically less than 1 .mu.m), the precision and uniformity requirements associated with the planarization step will likely limit yield.
Thus, notwithstanding these attempts to form power devices such as DMOS-based FETs and IGBTs, there continues to be a need for improved methods of forming power devices which are less susceptible to yield-limiting process steps such as planarization.